Substrate Resistance Extraction for Physics-based Layout Verification
@inproceedings{Smedes1993SubstrateRE,
title={Substrate Resistance Extraction for Physics-based Layout Verification},
author={Theo Smedes},
year={1993}
}Resistive coupling effects via the substrate may damage circuit behaviour of VLSI chips. In order to analyze the influence of the substrate on the circuit behaviour of VLSI chips the admittance matrix of the substrate must be known. This paper describes a Boundary Element Method for the calculation of this matrix. The method uses a Green’s function for the bounded 3D medium. The advantage of this approach is that only those parts of the boundary where current passes — such as substrate contacts…
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6 Citations
Substrate optimization based on semi-analytical techniques
- EngineeringIEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
- 1999
A three-dimensional Green's function-based boundary element method, accelerated through use of the fast Fourier transform, allows the computation of sensitivities with respect to all substrate parameters at a considerably higher speed than any methods reported in the literature.
Parasitics in VLSI Circuits and the Role of Layout Verification
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The behavior of IC interconnections and substrates, their electrical significance, and what constitutes an effective model for them are discussed, and the increased importance and new requirements of post-layout design verification are reviewed.
A Boundary Element Method for Substrate Cross-talk Analysis
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An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. Due to decreasing distances between components and…
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Substrate sensitivity analysis is used in a number of physical optimization tools, such as placement and trend analysis for the estimation of the impact of technology migration and/or layout re-design.
Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation
- EngineeringProceedings of the IEEE
- 2006
Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters…
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