• Corpus ID: 17986538

Substrate Resistance Extraction for Physics-based Layout Verification

  title={Substrate Resistance Extraction for Physics-based Layout Verification},
  author={Theo Smedes},
Resistive coupling effects via the substrate may damage circuit behaviour of VLSI chips. In order to analyze the influence of the substrate on the circuit behaviour of VLSI chips the admittance matrix of the substrate must be known. This paper describes a Boundary Element Method for the calculation of this matrix. The method uses a Green’s function for the bounded 3D medium. The advantage of this approach is that only those parts of the boundary where current passes — such as substrate contacts… 

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