Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation

  title={Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation},
  author={Ali Afzali-Kusha and Makoto Nagata and Nishath K. Verghese and David J. Allstot},
  journal={Proceedings of the IEEE},
Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise… CONTINUE READING
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