Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models

@inproceedings{Nagata2002SubstrateNA,
  title={Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models},
  author={Makoto Nagata and Yoshitaka Murasaka and Youichi Nishimori and Takashi Morie and Atsushi Iwata},
  booktitle={VLSI Design},
  year={2002}
}
This paper presents a substrate noise analysis methodology that employs chip-level substrate modeling based on F-matrix computation and digital substrate-noise injection modeling with a time-series divided parasitic capacitance model for time-domain power-supply current estimation.System-level simulation models generated accordingly to the methodology provide reliable substrate noise waveforms.Simulated waveforms for practical digital circuits on a 0.6-µm CMOS 4.5-mm square chip are well… CONTINUE READING

References

Publications referenced by this paper.

Physical design guides for substrate noise reduction in CMOS digital circuits

  • M. Nagata, J. Nagai, K. Hijikata, T. Morie, A. Iwata
  • IEEE J. Solid-State Circuits, 36(3):539–549, Mar…
  • 2001
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