Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation

Abstract

Due to interactions through the common silicon substrate, the layout and placement of devices and substrate contacts can have signi cant impacts on a circuit's ESD (Electrostatic Discharge) and latchup behavior in CMOS technologies. Proper substrate modeling is thus required for circuit-level simulation to predict the circuit's ESD performance and latchup… (More)
DOI: 10.1145/309847.309996

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