Submicron VLSI memory circuits

  title={Submicron VLSI memory circuits},
  author={T. Mano and J. Yamada and J. Inoue and S. Nakajima},
  journal={1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  • T. Mano, J. Yamada, +1 author S. Nakajima
  • Published 1983
  • Computer Science
  • 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
cell, alpha-induced soft-errors, are a serious problem. A solution is an on-chip ECC technique using bidirectional parity checking. A logic diagram of a RAM with on-chip ECC circuits is shown in Figure 1. In addition to (k x m) fundamental memory cells, (k tm) parity cells are connected with each word line. All of the cells along the same word line compose an ECC data set for bidirectional parity checking. Each element of this data in the fundamental memory cells belong t o two imaginary groups… Expand
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  • Computer Science
  • Proceedings of the IEEE
  • 1986
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