Sub-5nm All-Around Gate FinFET for Ultimate Scaling

@article{Lee2006Sub5nmAG,
  title={Sub-5nm All-Around Gate FinFET for Ultimate Scaling},
  author={Hyunjin Lee and Lee-Eun Yu and Seong-Wan Ryu and J. Han and K. Jeon and Dong-Yoon Jang and Kuk-Hwan Kim and Jiye Lee and Ju-Hyun Kim and S. Jeon and G. S. Lee and J. Oh and Yun-Chang Park and Woo Ho Bae and Hee Mok Lee and J. Yang and Jung Jae Yoo and Sang Ik Kim and Yang‐Kyu Choi},
  journal={2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.},
  year={2006},
  pages={58-59}
}
Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO2 shows an IDsat of 497muA/mum at VG=V D=1.0V. Characteristics of sub-5nm transistor are verified by using 3-D simulations as well as analytical models. A threshold voltage increases as the fin width reduces by quantum confinement effects. The threshold voltage shift was fitted to a theoretical model with consideration of the first-order perturbation theory. And… Expand

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References

Limits to binary logic switch scaling - a gedanken model
In this paper we consider device scaling and speed limitations on irreversible von Neumann computing that are derived from the requirement of "least energy computation." We consider computationalExpand