Sub-5nm All-Around Gate FinFET for Ultimate Scaling

  title={Sub-5nm All-Around Gate FinFET for Ultimate Scaling},
  author={H. Lee and Lee-Eun Yu and Seong-Wan Ryu and J. Han and K. Jeon and Dong-Yoon Jang and Kuk-Hwan Kim and J. Lee and J. Kim and Sang Cheol Jeon and G. S. Lee and Jae Sub Oh and Y. Park and Woo Ho Bae and H. M. Lee and J. Yang and Jung Jae Yoo and S. Kim and Y. Choi},
  journal={2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.},
  • H. Lee, Lee-Eun Yu, +16 authors Y. Choi
  • Published 2006
  • Engineering
  • 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.
  • Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO2 shows an IDsat of 497muA/mum at VG=V D=1.0V. Characteristics of sub-5nm transistor are verified by using 3-D simulations as well as analytical models. A threshold voltage increases as the fin width reduces by quantum confinement effects. The threshold voltage shift was fitted to a theoretical model with consideration of the first-order perturbation theory. And… CONTINUE READING

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