Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions

@article{Ono1993Sub50NG,
  title={Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions},
  author={M. Ono and M. Saito and T. Yoshitomi and C. Fiegna and T. Ohguro and H. Iwai},
  journal={Proceedings of IEEE International Electron Devices Meeting},
  year={1993},
  pages={119-122}
}
  • M. Ono, M. Saito, +3 authors H. Iwai
  • Published 1993
  • Materials Science
  • Proceedings of IEEE International Electron Devices Meeting
Forty-nanometer gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. To achieve such shallow junctions, a technique of solid-phase diffusion (SPD) from phosphorous-doped silicated glass (PSG) gate sidewalls is used. The resulting 40 nm gate length n-MOSFETs operate quite normally at room temperature. Even in the sub-50 nm region, short-channel effects-V/sub th/ shift and S-factor degradation-are suppressed very well. The impact… Expand
FABRICATION OF 40-150 NM GATE LENGTH ULTRATHIN N-MOSFETS USING EPITAXIAL LAYER TRANSFER SOI WAFERS
We have successfully fabricated 40–150-nm-gate-length ultrathin silicon-on-insulator (SOI) n-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) using SOI wafers prepared by theExpand
Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs
We have investigated short-channel effects of ultrathin (4-18-nm thick) silicon-on-insulator (SOI) n-channel MOSFET's in the 40-135 nm gate length regime. It is experimentally and systematicallyExpand
Short channel characteristics of Si MOSFET with extremely shallow source and drain regions formed by inversion layers
The influence of extremely shallow source and drain junctions on the short channel effects of Si MOSFET's are experimentally investigated. These extremely shallow junctions are realized in MOSFET'sExpand
Transistor characteristics of 14-nm-gate-length EJ-MOSFETs
We have fabricated electrically variable shallow junction metal-oxide-silicon field-effect transistors (EJ-MOSFETs) to investigate transport characteristics of ultrafine gate MOSFETs. By using EBExpand
Transistor operation of 30-nm gate-length EJ-MOSFETs
We have fabricated electrically variable shallow junction metal-oxide-silicon field-effect transistors (EJ-MOSFET's) to investigate transistor characteristics of ultrafine-gate MOSFET's. By using EBExpand
Transistor operations in 30-nm-gate-length EJ-MOSFETs
Discusses fabrication of electrically variable shallow junction MOSFETs (EJ-MOSFETs) to investigate transistor characteristics in ultra-fine gate MOSFETs. By using electron beam (EB) lithography andExpand
Tunneling gate oxide approach to ultra-high current drive in small geometry MOSFETs
  • H. Momose, M. Ono, +4 authors H. Iwai
  • Materials Science
  • Proceedings of 1994 IEEE International Electron Devices Meeting
  • 1994
Ultra-high performance n-MOSFETs were fabricated with a tunneling gate oxide 1.5 nm thick. It was found that these devices operate well when the gate length is around 0.1 /spl mu/m, because gateExpand
Short-channel-effect-suppressed sub-0.1-/spl mu/m grooved-gate MOSFET's with W gate
Grooved-gate Si MOSFET's with tungsten gates are fabricated using conventional manufacturing technologies, and their short-channel-effect-free characteristics are verified down to a source and drainExpand
CMOS device technology toward 50 nm region-performance and drain architecture
  • A. Hori, B. Mizuno
  • Physics
  • International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)
  • 1999
The continued scaling of Si MOSFET faces many critical issues. In this paper, the authors discuss drain architecture in relation to performance and the possibility of sub-0.1 /spl mu/m CMOS devices.Expand
Use of elevated source/drain structure in sub-0.1 um NMOSFETs
As MOSFET feature sizes are scaled down to 0.1 micrometers and below, new techniques are required to develop and fabricate shallow, low contact resistance, and low leakage S/D junctions. In thisExpand
...
1
2
3
4
5
...

References

SHOWING 1-9 OF 9 REFERENCES
High performance 0.1- mu m room temperature Si MOSFETs
The design and implementation of 0.15- mu m-channel N-MOSFETs with very high current drive and good short channel behavior at room temperature are discussed. Measured subthreshold characteristicsExpand
An SPDD p-MOSFET structure suitable for 0.1 and sub 0.1 micron channel length and its electrical characteristics
A new solid-phase diffused drain (SPDD) structure has been developed for 0.1 and sub-0.1 um p-MOSFET technology. Highly doped ultra-shallow p/sup +/ source and drain junctions were achieved byExpand
Performance and hot-carrier reliability of deep-submicrometer CMOS
  • T. Chan, H. Gaw
  • Materials Science
  • International Technical Digest on Electron Devices Meeting
  • 1989
Results of a comprehensive study of the performance and hot-carrier reliability of CMOS devices with channel length ranging from submicrometer to deep-submicrometer are presented. It is found thatExpand
Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's
The first device performance results are presented from experiments designed to assess FET technology feasibility in the 0.1-µm gate-length regime. Low-temperature device design considerations forExpand
A New Scaling Methodology For The 0.1 - 0.025/spl mu/m MOSFET
INTRODUCTION Recent developments of Si technology led to the fabrication of MOSFET:; with LG < 0.1pm [I]. This work provides for the first time a systematic investigation on the feasibility of suchExpand
Deep-submicrometer MOS device fabrication using a photoresist-ashing technique
A photoresist-ashing process has been developed which, when used in conjunction with conventional g-line optical lithography, permits the controlled definition of deep-submicrometer features. TheExpand
0.1 mu m CMOS devices using low-impurity-channel transistors (LICT)
Summary form only given. It was found that LICTs are very effective for providing low threshold voltages with good turn-offs in 0.1 mu m CMOS devices. Attention is given to device fabricationExpand
T.Hashimoto, Y.Sudoh, H.Kurino, A.Narai, S.Yokoyama, Y.Horiike, and M. Koyanagi, "3V operation of 70nm gate length MOSFET with new double punchthrough
  • Ing.Conf. on Solid State Devices and Materials,
  • 1992