Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions

  title={Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions},
  author={M. Ono and M. Saito and T. Yoshitomi and C. Fiegna and T. Ohguro and H. Iwai},
  journal={Proceedings of IEEE International Electron Devices Meeting},
  • M. Ono, M. Saito, +3 authors H. Iwai
  • Published 1993
  • Materials Science
  • Proceedings of IEEE International Electron Devices Meeting
Forty-nanometer gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. To achieve such shallow junctions, a technique of solid-phase diffusion (SPD) from phosphorous-doped silicated glass (PSG) gate sidewalls is used. The resulting 40 nm gate length n-MOSFETs operate quite normally at room temperature. Even in the sub-50 nm region, short-channel effects-V/sub th/ shift and S-factor degradation-are suppressed very well. The impact… Expand
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