Sub 50-nm FinFET: PMOS

@article{Huang1999Sub5F,
  title={Sub 50-nm FinFET: PMOS},
  author={Xuejue Huang and Wen-Chin Lee and Charles Kuo and Digh Hisamoto and Leland Chang and Jakub Kedzierski and Erik H. Anderson and Hideki Takeuchi and Yang‐Kyu Choi and K. Asano and Vivek Subramanian and Tsu-Jae King and Jeffrey Bokor and Chenming Hu},
  journal={International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)},
  year={1999},
  pages={67-70}
}
High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOS FinEET has an I/sub dsat/ of 410 /spl mu/A//spl mu/m (or 820 /spl mu/A//spl mu/m depending on the definition of the width of a double-gate device) at Vd=Vg=1.2 V and Tox=2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the… 

Figures from this paper

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI

Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short

FinFET scaling to 10 nm gate length

While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability

SOI devices for sub-0.1 /spl mu/m gate lengths

Different SOI MOSFET structures for sub 0.1 /spl mu/m gate lengths are discussed. To reduce short-channel effects such as DIBL (drain induced barrier lowering) and subthreshold slope degradation,

Characteristics of body-tied triple-gate pMOSFETs

Body-tied triple-gate pMOSFETs were fabricated using bulk Si wafers and characterized. Process steps to implement the devices are explained briefly. Device characteristics of the triple-gate pMOSFETs

Reduction of Short-Channel Effects in FinFET

An application of FinFET Technology has opened new development in Nano-technology. Simulations show that FinFET structure should be scalable down to 10 nm. Formation of ultra thin fin enables

Extension and source/drain design for high-performance FinFET devices

Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled

32 nm Gate Length FinFET: Impact of Doping

The design, fabrication and physical characteristics of n-channel FinFET with physical gate length of 32nm using visual TCAD (steady state analysis) are reported and the impact of doping concentration on the Performance is elucidated.

Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width

The FinFET transistor structure assures to rejuvenate the chip industry by rescuing it from the short-channel effects that limits the device scalability endured by current planar transistor
...

References

SHOWING 1-6 OF 6 REFERENCES

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si/sub 0.4/Ge/sub 0.6/ as

A folded-channel MOSFET for deep-sub-tenth micron era

Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel folded channel transistor structure is proposed. The quasi-planar

A comparative study of advanced MOSFET concepts

Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been the major device for integrated circuits over the past two decades. With technology advancement, there have been numerous MOSFET

Electrical properties of heavily doped polycrystalline silicon-germanium films

The electrical properties of polycrystalline silicon-germanium (poly-Si/sub 1/spl minus/x/Ge/sub x/) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented.

Work function of boron-doped polycrystalline Si/sub x/Ge/sub 1-x/ films

The work function of p-type polycrystalline Si/sub x/Ge/sub 1-x/ films deposited by LPCVD using SiH/sub 4/ and GeH/sub 4/ was determined by CV measurements on MOS structures. Boron was introduced in

Figure 12: Comparison between simulation data and experimental data

  • Figure 12: Comparison between simulation data and experimental data