Sub 50-nm FinFET: PMOS

  title={Sub 50-nm FinFET: PMOS},
  author={Xuejue Huang and Wen-Chin Lee and Charles Kuo and Digh Hisamoto and Leland Chang and Jakub Kedzierski and Erik H. Anderson and Hideki Takeuchi and Yang‐Kyu Choi and K. Asano and Vivek Subramanian and Tsu-Jae King and Jeffrey Bokor and Chenming Hu},
  journal={International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)},
High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOS FinEET has an I/sub dsat/ of 410 /spl mu/A//spl mu/m (or 820 /spl mu/A//spl mu/m depending on the definition of the width of a double-gate device) at Vd=Vg=1.2 V and Tox=2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the… 

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  • Figure 12: Comparison between simulation data and experimental data