Sub-20 nm CMOS FinFET technologies

@article{Choi2001Sub20NC,
  title={Sub-20 nm CMOS FinFET technologies},
  author={Yang‐Kyu Choi and N. Lindert and P. Xuan and S. Tang and Daewon Ha and E. Anderson and T. King and J. Bokor and C. Hu},
  journal={International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)},
  year={2001},
  pages={19.1.1-19.1.4}
}
  • Yang‐Kyu Choi, N. Lindert, +6 authors C. Hu
  • Published 2001
  • Materials Science, Engineering
  • International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)
A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current. 

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