Sub-20 nm CMOS FinFET technologies

  title={Sub-20 nm CMOS FinFET technologies},
  author={Yang‐Kyu Choi and N. Lindert and P. Xuan and S. Tang and Daewon Ha and E. Anderson and T. King and J. Bokor and C. Hu},
  journal={International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)},
  • Yang‐Kyu Choi, N. Lindert, +6 authors C. Hu
  • Published 2001
  • Materials Science, Engineering
  • International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)
A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current. 

Figures from this paper

Exploring ESD challenges in sub-20-nm bulk FinFET CMOS technology nodes
Bulk FinFET is the main technology option for sub 20-nm CMOS nodes. However, newly introduced process options in advanced bulk FinFET technologies can result in significant deterioration of intrinsicExpand
Reliability study of CMOS FinFETs
Hot-carrier and oxide reliability of CMOS FinFETs with 2.1 nm-thick gate-SiO/sub 2/ were investigated. It was found that hot-carrier immunity improves as the fin width (body thickness) decreases,Expand
Nanoscale FinFETs for low power applications
Abstract N and p channel FinFETs with fin widths in the range of 15–30 nm and gate lengths down to 20 nm have been processed using e-beam-lithography and nano-etching. The I On – I OffExpand
Extension and source/drain design for high-performance FinFET devices
Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. AngledExpand
Demonstration of FinFET CMOS circuits
We present, to our knowledge, the first published experimental demonstration of a CMOS inverter chain built from FinFETs, completely integrated in 180nm CMOS technology, using one level of copperExpand
FinFET for Terabit Era
A FinFET, a novel double-gate device structure is capable of scaling well into the nanoelectronics regime. High-performance CMOS FinFETs , fully depleted silicon-on-insulator (FDSOI) devices haveExpand
Analytical Modeling of Nanoscale Double Gate FinFET Device
FinFET is a novel double-gate device structure for future device design, modeling and circuit simulation purposes. FinFET have high-performance and low leakage, fully depleted silicon-on-insulatorExpand
30 nm self-aligned FinFET with large source/drain fan-out structure
A 30 nm self-aligned FinFET with a large single-crystalline source/drain structure is proposed and has been fabricated. The fabricated FinFET shows large intrinsic transconductance of 1070 µS/µm atExpand
Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension
We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristicsExpand
Extremely scaled silicon nano-CMOS devices
Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated downExpand


Quasi-planar NMOS FinFETs with sub-100 nm gate lengths
Double-gate MOSFETs alleviate short channel effects and allow for more aggressive device scaling. Simulations have shown that scaling double-gated devices can reach 10 nm. In the past, processExpand
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si/sub 0.4/Ge/sub 0.6/ asExpand
Sub 50-nm FinFET: PMOS
High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOSExpand
Patterning sub-30-nm MOSFET gate with i-line lithography
We have investigated two process techniques: resist ashing and oxide hard mask trimming. A combination of ashing and trimming produces sub-30-nm MOSFET gates. These techniques require neitherExpand
Ultra-thin body PMOSFETs with selectively deposited Ge source/drain
Ultra-thin body (UTB) MOSFETs with body thickness down to 4 nm and LPCVD selectively deposited Ge raised source and drain (S/D) are demonstrated for the first time. Devices with gate length down toExpand
Matching analysis of deposition defined 50-nm MOSFET's
NMOS- and PMOS-transistors with geometries down to 50 nm are fabricated by conventional optical lithography using a deposition- and etchback technique for masking the polysilicon layer. TheExpand
This paper describes computer simulations of various SOI MOSFETs with double and triple gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewallsExpand
Selective chemical etching of polycrystalline SiGe alloys with respect to Si and SiO2
Polycrystalline SiGe etches that are selective to silicon dioxide as well as silicon are needed for flexibility in device fabrication. A solution of NH4OH, H2O2, and H2O has been found to selectivityExpand
Characterization of surface mobility on the sidewalls of dry-etched trenches
The mobility on the sidewalls of the etched trenches was measured for electrons and holes for two surface orientation, for two different trench etch processes, and for various post-etch treatments.Expand
Process dependence of the SiO2/Si(100) interface trap density of ultrathin SiO2 films
The interface trap density of states Dit of ultrathin SiO2 film has been investigated as a function of process variables. The process parameters used were oxidation temperature (1000–1200 °C), oxideExpand