Sub-10-nm planar-bulk-CMOS devices using lateral junction control

@article{Wakabayashi2003Sub10nmPD,
  title={Sub-10-nm planar-bulk-CMOS devices using lateral junction control},
  author={H. Wakabayashi and S. Yamagami and N. Ikezawa and A. Ogura and M. Narihiro and K. Arai and Y. Ochiai and K. Takeuchi and T. Yamamoto and T. Mogami},
  journal={IEEE International Electron Devices Meeting 2003},
  year={2003},
  pages={20.7.1-20.7.3}
}
Sub-10-nm planar-bulk-CMOS devices were clearly demonstrated by a lateral source/drain (S/D) junction control using the precisely-controlled gate-electrode, shallow source/drain extensions (SDE) and steep halo. Good cut-off characteristics were observed for n/pMOSFETs with the gate length of 5 nm at 0.4 V for the first time. 
View on IEEE
doi.org
62 Citations
Highly Influential Citations
1
Background Citations
21
Methods Citations
3
Results Citations
1

Figures and Tables from this paper

62 Citations

Citation Type

Citation Type

Comparison of Nanoscale Metal-Oxide-Semiconductor Field Effect Transistors
In this paper, electrical characteristics of nanoscale single-, double-, and all-around-gate silicon-On-insulator (SOI) devices are computational investigated by using a quantum mechanical… Expand
Future of CMOS technology
  • H. Iwai
  • Engineering
  • 2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)
  • 2004
Previously, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a… Expand
CMOS technology future
  • H. Iwai
  • Engineering
  • Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004.
  • 2004
Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a… Expand
A Comparative Study of Electrical Characteristic on Sub-10-nm Double-Gate MOSFETs
We explore the structure effect on electrical characteristics of sub-10-nm double-gate metal–oxide–semiconductor field-effect transistors (DG MOSFETs). To quantitatively assess the nanoscale DG… Expand
Scaling impact on design performance metric of sub-micron CMOS devices incorporated with halo
Leakages and short channel effects (SCE) impose challenges in the designing of CMOS devices as the device feature size enters the nanoscale regime. Advanced process design of CMOS devices are crucial… Expand
Novel devices and process for 32 nm CMOS technology and beyond
TLDR
The discussion on the research progress of high-k-metal gate and non-planar MOSFET-technologies that are suitable to 32 nm technology node and beyond is specified. Expand
Electrical characterization of Si nanowire field-effect transistors with semi gate-around structure suitable for integration
Abstract Silicon nanowire (Si NW) field-effect transistors with a semi gate-around structure suitable for integration have been fabricated using conventional CMOS processes. With the use of SiO 2… Expand
CMOS Scaling Analysis based on ITRS Roadmap by Three-dimensional Mixed-mode Device Simulation
In this paper, the circuit performances such as circuit delay, RF characteristics and SRAM static noise margin are presented. These analyses are performed by threedimensional device simulation using… Expand
Device Design Consideration for Nanoscale MOSFET Using Semiconductor TCAD Tools
  • T. C. Hong, R. Ismail
  • Materials Science
  • 2006 IEEE International Conference on Semiconductor Electronics
  • 2006
The evolution of metal-oxide-semiconductor field effect transistor (MOSFET) technology has been governed mainly by device scaling over the past twenty years. One of the key questions concerning… Expand
Characteristics Optimization of Sub-10 nm Double Gate Transistors
Double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs) have recently been of great interest in modern nanoelectronics community. Device channel length L, thickness of silicon… Expand
...
1
2
3
4
5
...

References

SHOWING 1-2 OF 2 REFERENCES
Sub-50-nm physical gate length CMOS technology and beyond using steep halo
Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are… Expand
Supply-voltage optimization for below-70-nm technology-node MOSFETs
A tradeoff between the performance and power consumption is discussed for below-70-nm technology-node MOSFETs, as a function of power-supply voltage. In order to optimize the supply voltage,… Expand