Sub-10-nm planar-bulk-CMOS devices using lateral junction control

@article{Wakabayashi2003Sub10nmPD,
  title={Sub-10-nm planar-bulk-CMOS devices using lateral junction control},
  author={Hitoshi Wakabayashi and Shigeharu Yamagami and Nobuyuki Ikezawa and Atsushi Ogura and M. Narihiro and Kohichi Arai and Yukinori Ochiai and Ken Takeuchi and T. Yamamoto and Tohru Mogami},
  journal={IEEE International Electron Devices Meeting 2003},
  year={2003},
  pages={20.7.1-20.7.3}
}
Sub-10-nm planar-bulk-CMOS devices were clearly demonstrated by a lateral source/drain (S/D) junction control using the precisely-controlled gate-electrode, shallow source/drain extensions (SDE) and steep halo. Good cut-off characteristics were observed for n/pMOSFETs with the gate length of 5 nm at 0.4 V for the first time. 

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