Sub-10-nm planar-bulk-CMOS devices using lateral junction control
@article{Wakabayashi2003Sub10nmPD, title={Sub-10-nm planar-bulk-CMOS devices using lateral junction control}, author={Hitoshi Wakabayashi and Shigeharu Yamagami and Nobuyuki Ikezawa and Atsushi Ogura and M. Narihiro and Kohichi Arai and Yukinori Ochiai and Ken Takeuchi and T. Yamamoto and Tohru Mogami}, journal={IEEE International Electron Devices Meeting 2003}, year={2003}, pages={20.7.1-20.7.3} }
Sub-10-nm planar-bulk-CMOS devices were clearly demonstrated by a lateral source/drain (S/D) junction control using the precisely-controlled gate-electrode, shallow source/drain extensions (SDE) and steep halo. Good cut-off characteristics were observed for n/pMOSFETs with the gate length of 5 nm at 0.4 V for the first time.
65 Citations
Comparison of Nanoscale Metal-Oxide-Semiconductor Field Effect Transistors
- Physics
- 2004
In this paper, electrical characteristics of nanoscale single-, double-, and all-around-gate silicon-On-insulator (SOI) devices are computational investigated by using a quantum mechanical…
Future of CMOS technology
- Engineering, Computer Science2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)
- 2004
Limiting and its possible causes for the downscaling of CMOS are discussed from many aspects.
CMOS technology future
- EngineeringProceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004.
- 2004
Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a…
A Comparative Study of Electrical Characteristic on Sub-10-nm Double-Gate MOSFETs
- EngineeringIEEE Transactions on Nanotechnology
- 2005
We explore the structure effect on electrical characteristics of sub-10-nm double-gate metal–oxide–semiconductor field-effect transistors (DG MOSFETs). To quantitatively assess the nanoscale DG…
Scaling impact on design performance metric of sub-micron CMOS devices incorporated with halo
- Engineering2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)
- 2015
Leakages and short channel effects (SCE) impose challenges in the designing of CMOS devices as the device feature size enters the nanoscale regime. Advanced process design of CMOS devices are crucial…
Novel devices and process for 32 nm CMOS technology and beyond
- EngineeringScience in China Series F: Information Sciences
- 2008
The discussion on the research progress of high-k-metal gate and non-planar MOSFET-technologies that are suitable to 32 nm technology node and beyond is specified.
Electrical characterization of Si nanowire field-effect transistors with semi gate-around structure suitable for integration
- Engineering
- 2010
CMOS Scaling Analysis based on ITRS Roadmap by Three-dimensional Mixed-mode Device Simulation
- Engineering, Computer Science
- 2004
In this paper, the circuit performances such as circuit delay, RF characteristics and SRAM static noise margin are presented by threedimensional device simulation using Mixed-mode option.
Device Design Consideration for Nanoscale MOSFET Using Semiconductor TCAD Tools
- Engineering2006 IEEE International Conference on Semiconductor Electronics
- 2006
The evolution of metal-oxide-semiconductor field effect transistor (MOSFET) technology has been governed mainly by device scaling over the past twenty years. One of the key questions concerning…
Characteristics Optimization of Sub-10 nm Double Gate Transistors
- Engineering
- 2003
Double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs) have recently been of great interest in modern nanoelectronics community. Device channel length L, thickness of silicon…
References
SHOWING 1-2 OF 2 REFERENCES
Sub-50-nm physical gate length CMOS technology and beyond using steep halo
- Engineering
- 2002
Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are…
Supply-voltage optimization for below-70-nm technology-node MOSFETs
- Engineering
- 2002
A tradeoff between the performance and power consumption is discussed for below-70-nm technology-node MOSFETs, as a function of power-supply voltage. In order to optimize the supply voltage,…