Sub-10-nm planar-bulk-CMOS devices using lateral junction control

  title={Sub-10-nm planar-bulk-CMOS devices using lateral junction control},
  author={H. Wakabayashi and S. Yamagami and N. Ikezawa and A. Ogura and M. Narihiro and K. Arai and Y. Ochiai and K. Takeuchi and T. Yamamoto and T. Mogami},
  journal={IEEE International Electron Devices Meeting 2003},
Sub-10-nm planar-bulk-CMOS devices were clearly demonstrated by a lateral source/drain (S/D) junction control using the precisely-controlled gate-electrode, shallow source/drain extensions (SDE) and steep halo. Good cut-off characteristics were observed for n/pMOSFETs with the gate length of 5 nm at 0.4 V for the first time. 

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