Sub-1 V process-compensated MOS current generation without voltage reference

Abstract

A sub-1 V process-compensated MOS current generation concept that does not require a reference voltage is presented. A theoretical model for the concept showing reduced sensitivity to variation in process parameters including gate oxide thickness and threshold voltage is derived. MOSFET device measurements and circuit simulation results show reduced process… (More)

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@article{Narendra2001Sub1VP, title={Sub-1 V process-compensated MOS current generation without voltage reference}, author={Sudeep Chenna Narendra and Daniel Klowden and Vivek De}, journal={2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)}, year={2001}, pages={143-144} }