Study on Influence of Device Structure Dimensions and Profiles on Charge Collection Current Causing SET Pulse Leading to Soft Errors in Logic Circuits

@article{Tanaka2009StudyOI,
  title={Study on Influence of Device Structure Dimensions and Profiles on Charge Collection Current Causing SET Pulse Leading to Soft Errors in Logic Circuits},
  author={Katsuhiko Tanaka and Hideyuki Nakamura and Taiki Uemura and Kan Takeuchi and Toshikazu Fukuda and Shigetaka Kumashiro},
  journal={2009 International Conference on Simulation of Semiconductor Processes and Devices},
  year={2009},
  pages={1-4}
}
Current responses due to the strike of ionized particle onto nMOS transistor of 90nm and 55nm generation have been analyzed through 3D device simulations. From the current response, duration of charge collection (tcc) is determined, which correlated strongly with the width of erroneous pulse (SET pulse). Causes of the difference between tcc values of 90nm and 55nm generation MOSFETs have been investigated and it is found that the difference in STI depth and width of p-well contact line between… CONTINUE READING

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