Study of Design Factors Affecting Turn-on Time of Silicon Controlled Rectifiers (SCRS) in 90 and 65nm Bulk CMOS Technologies

@article{Sarro2006StudyOD,
  title={Study of Design Factors Affecting Turn-on Time of Silicon Controlled Rectifiers (SCRS) in 90 and 65nm Bulk CMOS Technologies},
  author={J. P. Di Sarro and Kiran V. Chatty and Robert Gauthier and Elyse Rosenbaum},
  journal={2006 IEEE International Reliability Physics Symposium Proceedings},
  year={2006},
  pages={163-168}
}
We explore the effect of layout factors on the turn-on time of silicon controlled rectifiers (SCRs) in 90nm and 65nm bulk CMOS technologies. Using a very fast transmission line pulse (VFTLP) tester, we show that a SCR in 65nm bulk CMOS technology can achieve a turn-on time of 500ps with proper design. Using device simulations, we identify factors limiting SCR turn-on time and provide a basis for the presented experimental results 

Citations

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Showing 1-10 of 28 extracted citations

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View 7 Excerpts
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View 5 Excerpts
Highly Influenced

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View 4 Excerpts
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View 1 Excerpt

References

Publications referenced by this paper.
Showing 1-10 of 10 references

C

G. Boselli, J. Rodriguez
Duvvury and J. Smith, “Analysis of ESD Protection Components in 65nm CMOS Technology: Scaling Perspective and Impact on ESD Design Window,” Proc. EOS/ESD Symposium, pp. 43-52 • 2005
View 1 Excerpt

K

C. Brennan, S. Chang, M. Woo
Chatty and R. Gauthier, “Implementation of Diode and Bipolar Triggered SCRs for CDM Robust ESD Protection in 90nm CMOS ASICS,” Proc. EOS/ESD Symposium, pp. 380-386 • 2005
View 1 Excerpt

R

K. Chatty, R. Gauthier, C. Putnam, M. Muhammad, M. Woo
Halbach and C. Seguin, “Study of Factors Limiting ESD Diode Performance in 90nm CMOS Technologies and Beyond,” Proc. Intl. Reliability Physics Symposium, pp. 98- 105 • 2005
View 1 Excerpt

VF-TLP systems using TDT and TDRT for kelvin wafer measurements and package level testing

2004 Electrical Overstress/Electrostatic Discharge Symposium • 2004
View 1 Excerpt

B

M. Mergens, C. Russ, +3 authors R. Mohn
Keppens and S. Trinh, “Diode-Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGE HBTs and CMOS Ultra-Thin Gate Oxides,” IEDM, pp. 515-518 • 2003
View 1 Excerpt

Novel Diode-Chain Triggering SCR Circuits for ESD Protection,

S. L. Jang, M. S. Gau, C. K. Lin
Solid-State Electronics, • 2000
View 1 Excerpt

Latchup in CMOS technologies

IEEE Circuits and Devices Magazine • 1987
View 1 Excerpt