Study of CMOS Process Variation by Multiplexing Analog Characteristics

  title={Study of CMOS Process Variation by Multiplexing Analog Characteristics},
  author={K. Gettings and D. Boning},
  journal={IEEE Transactions on Semiconductor Manufacturing},
Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit performance. In this paper we address this need by contributing a test circuit methodology for the extraction of spatial, layout and size dependent variations at both device and interconnect levels. The test chip uses a… CONTINUE READING


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