Study of "Look-Aside" Memory

@article{Lee1969StudyO,
  title={Study of "Look-Aside" Memory},
  author={Francis F. Lee},
  journal={IEEE Transactions on Computers},
  year={1969},
  volume={C-18},
  pages={1062-1064}
}
  • F. Lee
  • Published 1 November 1969
  • Psychology, Biology
  • IEEE Transactions on Computers
A small, but fast, associative memory can be used in a "look-aside" manner to improve the overall memory performance of a computer. For a 128-cell 100-ns associate memory working with a 1-us main memory, the effective memory cycle time is reduced to between 350-to 400-ns. 

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References

SHOWING 1-4 OF 4 REFERENCES
Design of Univac®-LARC system: I
This talk is a progress report and in many respects a final report on the Univac® --- LARC system which has been developed by Remington Rand Univac. It is a companion not only to another talk on LARC
Considerations in the design of a computer with high logic - to - memory speed ratio , " Proc . Gigacycle Computing Systems , January 29 - February 2 , 1962
    Considerations in the design of a computer with high logic-to-memory speed ratio
    • Proc. Gigacycle Computing Systems, January 29-February 2, 1962. AIEE Special Publ. S-136, pp. 53-63.
    • 1962
    Lookaside memory implementation
    • Project MAC Memorandum MAC-M-99, August 19, 1963. 1.0 V 0.8 0.6 a 0.4 0.2 Ar .0 0.8 0.6 a 0.4 0.2 1064 1.
    • 1963