Studies and Performance Evaluation of Vedic Multiplier using Fast Adders

@inproceedings{Rao2014StudiesAP,
  title={Studies and Performance Evaluation of Vedic Multiplier using Fast Adders},
  author={Y. Narasimha Rao and Vara Prasada and Penmetsa V. Krishna Raja},
  year={2014}
}
In many generic systems it is challenging to reduce the load resulted by many coprocessors, which are used to provide special functions like arithmetic operations, signal processing and many other applications. The speed of processors or coprocessors mainly depends on its internal arithmetic circuits like multipliers in ALU. Many signal processing and scientific computers are demanding multiple number of high speed multipliers on single chip. But this increasing instruction cycle time which… CONTINUE READING

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Comparative study of performance vedic multiplier on the basis of adders used

  • 2015 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE)
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