Structural Fault Based Specification Reduction for Testing Analog Circuits

  title={Structural Fault Based Specification Reduction for Testing Analog Circuits},
  author={Soon-Jyh Chang and Chung-Len Lee and Jwu E. Chen},
  journal={J. Electronic Testing},
Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is… CONTINUE READING


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