Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

Abstract

This paper addresses key technical and economic issues in the design of on-chip measurement circuitry that can be utilized to reduce the cost of testing. A brief outline is provided for research work related to analog/RF built-in self- test (BIST), on-chip instrumentation, and testing requirements of RF front-end blocks. The overview is intended to present… (More)

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