Statistical timing verification for transparently latched circuits through structural graph traversal

@article{Yuan2010StatisticalTV,
  title={Statistical timing verification for transparently latched circuits through structural graph traversal},
  author={Xingliang Yuan and Jia Wang},
  journal={2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)},
  year={2010},
  pages={663-668}
}
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will adapt random delays at runtime due to time borrowing. The central problem to determine the timing yield is to compute the probability of the presence of a positive cycle in the latest latch timing graph. Existing algorithms are either optimistic since cycles are omitted or require iterations that cannot be polynomially… CONTINUE READING

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