Statistical timing analysis driven post-silicon-tunable clock-tree synthesis

@article{Tsai2005StatisticalTA,
  title={Statistical timing analysis driven post-silicon-tunable clock-tree synthesis},
  author={Jeng-Liang Tsai and Lizheng Zhang},
  journal={ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.},
  year={2005},
  pages={575-581}
}
Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock tuning. Existing design approaches for post-silicon-tunable (PST) clock-tree synthesis usually insert a PST clock buffer for each flip-flop or put PST clock buffers across an entire level of a clock-tree. This can cause significant over-design and long tuning time. In this paper, we propose to insert PST clock buffers at… CONTINUE READING
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