Statistical modeling and post manufacturing configuration for scaled analog CMOS

  title={Statistical modeling and post manufacturing configuration for scaled analog CMOS},
  author={G{\"o}kçe Keskin and Jonathan E. Proesel and Lawrence T. Pileggi},
  journal={IEEE Custom Integrated Circuits Conference 2010},
Process variations in advanced CMOS process nodes limit the benefits of scaling for analog designs. In the presence of increasing random intra-die variations, mismatch becomes a significant design challenge in circuits such as comparators. In this paper we describe and demonstrate the details of a statistical element selection (SES) methodology that relies on choosing a subset of selectable circuit elements (e.g., input transistors in a comparator) to achieve the desired specification (e.g… CONTINUE READING
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