Statistical logic cell delay analysis using a current-based model

@article{Fatemi2006StatisticalLC,
  title={Statistical logic cell delay analysis using a current-based model},
  author={Hanif Fatemi and Shahin Nazarian and Massoud Pedram},
  journal={2006 43rd ACM/IEEE Design Automation Conference},
  year={2006},
  pages={253-256}
}
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can accurately compute the output waveform for input waveforms of arbitrary shapes subjected to noise. The cell parasitic capacitances are pre-characterized by lookup tables to improve the accuracy. To capture the effect of process parameter variations on the cell behavior, the output voltage waveform of logic cells is… CONTINUE READING

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