Static Test Compaction for Scan-Based Designs to Reduce Test Application Time

@article{Pomeranz1998StaticTC,
  title={Static Test Compaction for Scan-Based Designs to Reduce Test Application Time},
  author={Irith Pomeranz and Sudhakar M. Reddy},
  journal={Journal of Electronic Testing},
  year={1998},
  volume={16},
  pages={541-552}
}
We propose a static compaction procedure to reduce the test application time for full and partial scan synchronous sequential circuits. The procedure accepts as input a set of test subsequences. A test subsequence consists of a sequence of primary input vectors, and a vector to be scanned-in before the input sequence is applied. The procedure uses two operations to reduce the test application time. The first operation combines test subsequences. The second operation reduces the lengths of the… CONTINUE READING

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