Corpus ID: 59865353

State Machine Coding Styles for Synthesis

@inproceedings{Cummings2002StateMC,
  title={State Machine Coding Styles for Synthesis},
  author={Clifford E. Cummings},
  year={2002}
}
This paper details efficient Verilog coding styles to infer synthesizable state machines. HDL considerations such as advantages and disadvantages of one-always block FSMs Vs. two-always block FSMs are described. 
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