Corpus ID: 59865353

State Machine Coding Styles for Synthesis

  title={State Machine Coding Styles for Synthesis},
  author={Clifford E. Cummings},
This paper details efficient Verilog coding styles to infer synthesizable state machines. HDL considerations such as advantages and disadvantages of one-always block FSMs Vs. two-always block FSMs are described. 
Coding Techniques in Verilog for Finite State Machine Designs in FPGA
Coding techniques in Verilog HDL of finite state machines (FSMs) for synthesis in field programmable gate arrays (FPGAs) are researched, and the choice problem the best FSM coding styles in terms ofExpand
Clocking Schedule And Writing Vhdl Programs For Synthesis
The essence of modeling digital functions is described and a powerful concept, called clocking schedule, for writing a VHDL program for RTL and logic synthesis is presented, which facilitates seamless integration of all the modules in a digital design. Expand
Power Optimization of AHB Slave-SPI Master with RTL Clock Gating
SPI (Serial Peripheral Interface) is a serial interface which facilitates the synchronous serial data transfer between 2 devices. It operates in master and slave modes. AMBA (Advanced MicrocontrollerExpand
Coherent minimisation : aggressive optimisation for symbolic finite state transducers
The main result of this thesis is that the coherent minimisation is sound and compositional, and in order to support more realistic applications to hardware synthesis, a refined model of transducers is introduced, which is called symbolic finite states transducers that can model systems which involve very large or infinite data-types. Expand


State Machine Design Techniques for Verilog and VHDL
A finite state machine has the general structure shown in Figure 1, a set of n flip-flops clocked by a single clock signal (hence “synchronous” state machine). Expand
Verilog nonblocking assignments demystified
  • Clifford E. Cummings
  • Computer Science
  • Proceedings International Verilog HDL Conference and VHDL International Users Forum
  • 1998
This paper examines many of the misunderstandings surrounding nonblocking assignments and how non blocking assignments are appropriately used in behavioral and RTL-synthesis modeling. Expand
HDL Chip Design
  • Doone Publications, Madison, Alabama, 1997, pp. 193-270.
  • 1997