Standby power reduction using dynamic voltage scaling and canary flip-flop structures

@article{Calhoun2004StandbyPR,
  title={Standby power reduction using dynamic voltage scaling and canary flip-flop structures},
  author={B. H. Calhoun and A. P. Chandrakasan},
  journal={IEEE Journal of Solid-State Circuits},
  year={2004},
  volume={39},
  pages={1504-1511}
}
Lowering V/sub DD/ during standby mode reduces power by decreasing both voltage and current. Analysis of flip-flop structures shows how low the voltage can scale before destroying the state information. Measurements of a 0.13-/spl mu/m, dual-V/sub T/ test chip show that reducing V/sub DD/ to near the point where state is lost gives the best power savings. We show that "canary" flip-flops provide a mechanism for observing the proximity to failure for the flip-flops. The canary flip-flops enable… CONTINUE READING
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