Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

@article{Jeon2010StandbyLP,
  title={Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems},
  author={HeungJun Jeon and Yong-bin Kim and Minsu Choi},
  journal={IEEE Transactions on Instrumentation and Measurement},
  year={2010},
  volume={59},
  pages={1127-1133}
}
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the adaptive optimal reverse body-bias voltage. The adaptive optimal body-bias voltage is generated from the proposed leakage monitoring circuit, which compares the subthreshold current (I SUB) and the band-to-band tunneling (BTBT) current (I BTBT). The proposed circuit was simulated in HSPICE using 32-nm bulk CMOS… 
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