Standard cell level parasitics assessment in 20nm BPL and 14nm BFF

@article{Schuddinck2012StandardCL,
  title={Standard cell level parasitics assessment in 20nm BPL and 14nm BFF},
  author={P. Schuddinck and Mustafa Badaroglu and Michele Stucchi and S. Demuynck and Andriy Hikavyy and M. Garcia-Bardon and Abdelkarim Mercha and Arindam Mallik and Thomas Chiarella and S. Kubicek and Raja Athimulam and Nadine Collaert and Naoto Horiguchi and I. Debusschere and Aaron V.-Y. Thean and Laith Altimime and Diederik Verkest},
  journal={2012 International Electron Devices Meeting},
  year={2012},
  pages={25.3.1-25.3.4}
}
It is shown that the performance impact of middle-of-line (MOL) patterning process variations can be reduced by 30% by relaxing the standard cell gate pitch by 10% in both 20nm bulk planar (BPL) and 14nm bulk finFET (BFF). Tungsten can safely replace copper in local interconnect IM2, which allows the MOL critical dimensions (CD) to be reduced by 40% in 20nm BPL, resulting in 5% performance improvement. In 14nm BFF, 10% performance degradation can be traded in for 40% smaller IM1 contact area… CONTINUE READING

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