Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

@article{Zhu2014SplitSARAI,
  title={Split-SAR ADCs: Improved Linearity With Power and Speed Optimization},
  author={Yan Zhu and C. Chan and U. Chio and Sai-Weng Sin and U. Seng-Pan and R. Martins and F. Maloberti},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2014},
  volume={22},
  pages={372-383}
}
  • Yan Zhu, C. Chan, +4 authors F. Maloberti
  • Published 2014
  • Computer Science, Mathematics
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the… Expand
50 Citations
A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration
  • 2
The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction
  • 4
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC
  • 9
Analysis and optimization of the two-stage pipelined SAR ADCs
  • 1
  • PDF
Digital Calibration of Elements Mismatch in Multirate Predictive SAR ADCs
  • PDF
Static linearity BIST for $V_{cm}$-based switching SAR ADCs using a reduced-code measurement technique
  • Highly Influenced
  • PDF
...
1
2
3
4
5
...

References

SHOWING 1-10 OF 43 REFERENCES
Linearity analysis on a series-split capacitor array for high-speed SAR ADCs
  • 25
  • PDF
Parasitic calibration by two-step ratio approaching technique for split capacitor array SAR ADCs
  • 14
  • PDF
A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs
  • 12
  • PDF
A power-efficient capacitor structure for high-speed charge recycling SAR ADCs
  • 27
  • PDF
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
  • 482
  • PDF
Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs
  • 158
  • PDF
A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration
  • 162
Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC
  • 39
  • PDF
A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs
  • 9
  • PDF
A CMOS low-power ADC for DVB-T and DVB-H systems
  • 21
...
1
2
3
4
5
...