Spill code minimization via interference region spilling

  title={Spill code minimization via interference region spilling},
  author={P. Bergner and P. Dahl and David Engebretsen and M. O'Keefe},
  booktitle={PLDI '97},
  • P. Bergner, P. Dahl, +1 author M. O'Keefe
  • Published in PLDI '97 1997
  • Computer Science
  • Many optimizing compilers perform global register allocation using a Chaitin-style graph coloring algorithm. Live ranges that cannot be allocated to registers are spilled to memory. The amount of code required to spill the live range depends on the spilling heuristic used. Chaitin's spilling heuristic offers some guidance in reducing the amount of spill code produced. However, this heuristic does not allow the partial spilling of live ranges and the reduction in spill code is limited to a local… CONTINUE READING
    86 Citations
    Spill code minimization by spill code motion
    • 5
    A Framework for Enhancing Code Quality in Limited Register Set Embedded Processors
    • 8
    Register allocation and spilling using the expected distance heuristic
    Color Flipping
    • 1
    Fine-Grain Register Allocation Based on a Global Spill Costs Analysis
    • 2
    • PDF
    Register allocation and spill complexity under SSA
    • 26
    • PDF