Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization

@inproceedings{Sathyamurthy1995SpeedingUP,
  title={Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization},
  author={Harsha Sathyamurthy and Sachin S. Sapatnekar and John P. Fishburn},
  booktitle={ICCAD},
  year={1995}
}
Highly Cited
This paper has 32 citations. REVIEW CITATIONS

From This Paper

Topics from this paper.

Citations

Publications citing this paper.
Showing 1-10 of 12 extracted citations

Geometric Programming Formulation for Gate Sizing with Pipelining Constraints

2015 28th International Conference on VLSI Design • 2015
View 1 Excerpt

Variability mitigation using correction function technique

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS) • 2013
View 1 Excerpt

An Efficient Method for Large-Scale Gate Sizing

IEEE Transactions on Circuits and Systems I: Regular Papers • 2008