Speed and Power Optimization of FPGA’S Based on Modified Viterbi Decoder

Abstract

Advancement in the VlSI technology using low power, less area and high speed constraints is mostly used for encoding and decoding of data. In this paper power and cost reduction with increase in speed using viterbi decoder(VD) for trellis coded modulation(TCM) is proposed. Viterbi decoder uses viterbi algorithm for TCM decoding, but the efficient speed and power reduction is not achieved at the receiving ends. A pipelined architecture with a pre-computational approach which incorporated T-algorithm for VD is proposed in this paper. Priority encoder is used along with convolution encoders to send data bits of high priority first with a code rate of 1⁄2 in TCM system. The proposed architecture reduces power consumption of 80% without performance loss. The degradation of clock speed used in the architecture is negligible. Proposed architecture is simulated and synthesized using Xilinx ISE successfully and analyzed using FPGA Spartan-6 XC6SLX45 which is a low power target device. The results obtained are found to be consuming low power.

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Cite this paper

@inproceedings{VPrasanth2014SpeedAP, title={Speed and Power Optimization of FPGA’S Based on Modified Viterbi Decoder}, author={V.Prasanth and Rubia Tasneem}, year={2014} }