Specification and Verification of System-Level Hardware Designs using Timing Diagrams

Abstract

In this paper we present a novel approach to the specification and verification of system-level hardware designs. It is based on Timing Diagrams, a graphical specification language with an intuitive semantics, which is especially appropriate for the description of asynchronous distributed systems such as hardware designs. Timing Diagrams and their semantics are formally defined based on a translation to Temporal Logic. It is shown that for the resulting type of formulas there is an efficient modelchecking procedure, thus allowing fully automatic verification of hardware designs.

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@inproceedings{Schlr1993SpecificationAV, title={Specification and Verification of System-Level Hardware Designs using Timing Diagrams}, author={Rainer Schl{\"{o}r}, year={1993} }