• Corpus ID: 166228292

Specification and Reactive Synthesis of Robust Controllers

  title={Specification and Reactive Synthesis of Robust Controllers},
  author={Paritosh K. Pandya and Amol Wakankar},
This paper investigates the synthesis of robust controllers from logical specification of regular properties given in an interval temporal logic QDDC. Our specification encompasses both hard robustness and soft robustness. Here, hard robustness guarantees invariance of commitment under user-specified relaxed (weakened) assumptions. A systematic framework for logically specifying the assumption weakening by means of a formula, called Robustness Criterion, is presented. The soft robustness… 

Logical specification and uniform synthesis of robust controllers

A uniform method is presented for the synthesis of a robust controller which guarantees the invariance of specified hard robustness and it optimizes the expected value of occurrence of commitment across input sequences.

DCSynth: Guided Reactive Synthesis with Soft Requirements

The proposed technique for guided controller synthesis from regular requirements which are specified using an interval temporal logic QDDC is found to be well suited for guided synthesis due to its superiority in dealing with both qualitative and quantitative specifications.

Specification and Optimal Reactive Synthesis of Run-time Enforcement Shields

This paper gives a method for logical specification of shields using formulas of logic Quantified Discrete Duration Calculus (QDDC), consisting of a correctness requirement REQ as well as a hard deviation constraint HDC which must both be mandatorily and invariantly satisfied by the shield.

Verified Software. Theories, Tools, and Experiments: 11th International Conference, VSTTE 2019, New York City, NY, USA, July 13–14, 2019, Revised Selected Papers

This paper discusses the design of MOPSA, an ongoing effort to design a novel semantic static analyzer by abstract interpretation, and proposes a vision for a framework for managing uncertainty in assurance cases for software systems, by systematically identifying, assessing and addressing it.



DCSYNTH: A Tool for Guided Reactive Synthesis with Soft Requirements

It is shown that this soft requirement guided synthesis provides a useful ability to specify and efficiently synthesize high quality controllers and is also useful in dealing with conflicting requirements.

Robust discrete synthesis against unspecified disturbances

The theory and algorithmic tools for the design of robust discrete controllers for π-regular properties on discrete transition systems are presented and an application of the theory to theDesign of controllers that tolerate infinitely many transient errors provided they occur infrequently enough is shown.

Synthesizing robust systems

This article defines two robustness notions, combine them, and shows how to enforce them in synthesis of robust reactive systems from temporal specifications, and presents an implementation of a special case of robustness.

Supervisory control and reactive synthesis: a comparative introduction

A novel reduction of the basic supervisory control problem, non-blocking case, to a problem of reactive synthesis with plants and with a maximal permissiveness requirement is provided.

Resilience to intermittent assumption violations in reactive synthesis

The framework for achieving reactive systems that are robust against intermittent violations of their environment assumptions is presented, which builds on generalized reactivity(1) synthesis, a synthesis approach that is well-known to be scalable enough for many practical applications.

Control of Discrete Event Systems

The main focus of this paper is the presentation of the automata and formal language model for DES introduced by Raniadge and Wonham in 1985, suitable for the examination of some important control theoretic issues, and provides a good basis for modular synthesis of controllers.

Shield Synthesis: Runtime Enforcement for Reactive Systems

The first shield synthesis solution for reactive hardware systems is presented and the experimental results are reported, featuring an additional appendix.

Reactive Control Meets Runtime Verification: A Case Study of Navigation

This paper develops a layered control architecture where runtime monitors constructed from formal specifications are embedded into the navigation stack and uses temporal logic and regular expressions to describe safety requirements and mission specifications.

Formalizing Timing Diagram Requirements in Discrete Duration Calculus

This paper proposes a practically useful notation called SeCeNL which enhances the quantifier and negation free fragment of QDDC with features of nominals and limited liveness and gives a linear time translation from timing diagrams to SeCENL.

Supervisory control of a class of discrete event processes

The paper studies the control of a class of discrete event processes, i.e., processes that are discrete, asynchronous and possibly nondeterministic. The controlled process is described as the