Sparse matrix-vector multiply on the Texas Instruments C6678 Digital Signal Processor

Abstract

The Texas Instruments (TI) C6678 “Shannon” is TI’s most recently-released Digital Signal Processor (DSP). Although its original purpose was voice and video encoding and decoding, it may have the potential to become a practical coprocessor for scientific computing. In this paper, we evaluate the C6678 in terms of its programming methodology, performance, and power efficiency. As a case study, we implemented a sparse matrix vector multiply (SpMV) kernel and used it to perform a comparative study against the NVIDIA Kepler GK104 and GK106 Graphical Processor Units. On the DSP, we take advantage of many of the C6678’s features, including its VLIW and SIMD instruction set architecture, program-controlled scratchpad memory, and direct memory access (DMA) controller. We found that the DSP is unable to outperform the GPUs in raw performance but can achieve roughly equal power efficiency in Gflops/Watt. This is more impressive when considering that the DSP is manufactured in a 45 nm process while the GPUs are manufactured in a 28 nm process. We believe that subsequent DSPs, when manufacturered in a modern fabrication process, may be more competitive with GPUs in power efficiency. We also found that, for this kernel, the DSP is able to achieve higher utilization of both its peak memory bandwidth and its functional units as compared with the GPUs. In this paper we describe our kernel and the programming techniques required to optimize its performance. Keywords—high performance computing; sparse matrix vector (SpMV); linear algebra; digital signal processor (DSP); graphical processor unit (GPU); very long instruction word (VLIW)

DOI: 10.1109/ASAP.2013.6567571
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@inproceedings{Gao2013SparseMM, title={Sparse matrix-vector multiply on the Texas Instruments C6678 Digital Signal Processor}, author={Yang Gao and Jason D. Bakos}, booktitle={ASAP}, year={2013} }