Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing

  title={Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing},
  author={Takumi Maruyama and Toshio Yoshida and Ryuji Kan and Iwao Yamazaki and Shuji Yamamura and Noriyuki Takahashi and Mikio Hondou and Hiroshi Okano},
  journal={IEEE Micro},
The Sparc64 VIIIfx eight-core processor, developed for use in petascale computing systems, runs at speeds of up to 2 GHz and achieves a peak performance of 128 gigaflops while consuming as little as 58 watts of power. Sparc64 VIIIfx realizes a six-fold improvement in performance per watt over previous generation Sparc64 processors. 

Sparc64 XIfx: Fujitsu's Next-Generation Processor for High-Performance Computing

Sparc64 XIfx, the latest high-performance computing processor, includes a 34-core processor and achieves 1.1 teraflops of peak performance. This chip is designed for massive parallel supercomputer

SPARC64 XII: Fujitsu’s Latest 12-Core Processor for Mission-Critical Servers

The SPARC64 XII 12-core processor, developed for high-performance, mission-critical servers, runs at speeds of up to 4.35 GHz and achieves a peak performance of 417 GIPS and 835 Gflops. SPARC64 XII

SPARC64TM XII: Fujitsu's latest 12 core processor for mission critical servers

  • T. Maruyama
  • Computer Science
    2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
  • 2017
The design, microarchitecture, and performance of the latest Fujitsu SPARC64 XII 12 core microprocessor which has been developed for high performance, mission critical servers is described.

SPARC 64 VIIIfx : CPU for the K computer

The technologies used to achieve the high performance, low power consumption and high reliability of SPARC64 VIIIfx are outlined.

Past, Present, and Future of SPARC64 Processors

The history of the SPARC64 processor development, and the enhanced points of each generation, is described.

Sparc64 X: Fujitsu's New-Generation 16-Core Processor for Unix Servers

The authors enhanced the microarchitecture and introduced an extended instruction set called High-Performance Computing Arithmetic Computational Extensions (HPC-ACE), used previously in the K computer, to realize extremely high-throughput performance of Sparc64 X.

The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server

A 10th generation SPARC64 processor, fabricated in enhanced 28 nm CMOS, runs at 3.0 GHz and contains 16 cores with 24 MB shared L2 cache and system/DDR3/PCIe interfaces in 588 mm2 die area and SER reduction is observed by neutron irradiation experiments.

Multicore architecture optimizations for HPC applications

This thesis explores HPC-specific optimizations in order to make better utilization of the available transistors and to improve performance by transparently executing parallel code across multiple GPU accelerators, and investigates multi-socket NUMA GPU designs and shows that significant changes are needed to both the GPU interconnect and cache architectures to achieve performance scalability.

Use of SIMD Vector Operations to Accelerate Application Code Performance on Low-Powered ARM and Intel Platforms

This paper considers and compares the NEON SIMD instruction set used on the ARM Cortex-A series of RISC processors with the SSE2 SIMD Instruction set found on Intel platforms within the context of the Open Computer Vision (OpenCV) library.

An Analytical Model for Matrix Multiplication on Many Threaded Vector Processors

A parallel matrix multiplication algorithm is presented and an analytical performance model is built that was evaluated and critical configurations are given to guide the design of MTV processors.



A 1.3 GHz fifth generation SPARC64 microprocessor

  • H. AndoY. Yoshida H. Sugiyama
  • Computer Science
    2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
  • 2003
A fifth generation SPARC64 processor implemented in 130 nm CMOS process with 8 layers of Cu metallization operates with a 1.3 GHz clock and dissipates 34.7 W. The processor is a 4-issue out-of-order

SPARC64™ VII Fujitsu's next generation quad-core processor

  • T. Maruyama
  • Business
    2008 IEEE Hot Chips 20 Symposium (HCS)
  • 2008
This article consists of a collection of slides from the author's conference presentation on the Fujitsu SPARC64™ VII quad-core processor.

Fujitsu’s New Sparc64 V for Mission Critical Servers,’

  • Microprocessor Forum,
  • 2002

Low Power Design of a High Performance Quad-core Microprocessor for Mission Critical Servers,’

  • COOL Chips XII,
  • 2009