Electronic System Level has brought new abstractions for designing systems, which most designers are not familiar with. The Space CodesignTM SystemC design framework allows designers to easily model hardware/software-based systems, starting from a high level model and refining down to the chip. We propose a rapid system prototyping toolset that permits co-monitoring of specifications, effortless platform exploration for hardware/software partitioning and an automated co-synthesis for rapid FPGA implementation. We demonstrate the methodology by implementing the guiding system of a land rover application. More precisely, we focus on the architecture exploration effort by looking at the partitioning aspects using an IBM CoreConnect OPB bus cycle accurate model, and a MicroBlaze ISS. We collect different mapping results to guide the implementation down to a Xilinx Virtex-II Pro FPGA. Results prove that first working at the system level significantly helps in targeting an efficient hardware/software solution.