Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor

  title={Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor},
  author={Trevor Meyerowitz and Alberto L. Sangiovanni-Vincentelli and Mirko Sauermann and Dominik Langen},
  journal={2008 Design, Automation and Test in Europe},
A generic and retargetable tool flow is presented that enables the export of timing data from software running on a cycle-accurate Virtual Prototype (VP) to a concurrent functional simulator. First, an annotation framework takes information gathered from running an application on the VP and automatically annotates the line-level delays back to the original source code. Then, a SystemC-based timed functional simulator runs the annotated source code much faster than the VP while preserving timing… CONTINUE READING
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