Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology

@article{Lee2007SolderJL,
  title={Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology},
  author={Chang-Chun Lee and Chien-Chen Lee and Hsiao-Tung Ku and Shu-Ming Chang and Kuo-Ning Chiang},
  journal={Microelectronics Reliability},
  year={2007},
  volume={47},
  pages={196-204}
}
As the industry keeps moving towards further miniaturization of electronic devices, even smaller sizes, a lower economical cost, and higher reliability are not only convenient but have become a necessity of the design. A well-designed package structure can effectively restrain the solder joint fatigue failure induced by material coefficient of thermal expansion (CTE) mismatch. Wafer level chip scaling package (WLCSP) has a high potential for future advanced packaging. However, the solder joint… CONTINUE READING

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