Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology

  title={Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology},
  author={Chang-Chun Lee and Chien-Chen Lee and Hsiao-Tung Ku and Shu-Ming Chang and Kuo-Ning Chiang},
  journal={Microelectronics Reliability},
As the industry keeps moving towards further miniaturization of electronic devices, even smaller sizes, a lower economical cost, and higher reliability are not only convenient but have become a necessity of the design. A well-designed package structure can effectively restrain the solder joint fatigue failure induced by material coefficient of thermal expansion (CTE) mismatch. Wafer level chip scaling package (WLCSP) has a high potential for future advanced packaging. However, the solder joint… CONTINUE READING


Publications referenced by this paper.
Showing 1-10 of 13 references

A analysis of the reliability of a wafer level package (WLP) using a silicone under the bump (SUB) configuration

  • M Gonzalez, B Vandevelde, MV BuIcke, C Winters, E Beyne, YI Lee
  • Proceedings of 53rd electronic omponents and…
  • 2003
1 Excerpt

Parameterized modeling of thermomechanical reliability for CSP assemblies

  • B Vandevelde, E Beyne, GQ Zhang, J Caers, D Vandepitte, M. Baelmans
  • Trans ASME J Electron Packag 2003;125:498–505
  • 2003
1 Excerpt

Response surface modeling for nonlinear packaging stresses

  • WD van Driel, GQ Zhang, JHJ Janssen, LJ. Ernst
  • Trans ASME J Electron Packag 2003;125:490–7
  • 2003
2 Excerpts

Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)

  • JH Lau, Lee S-WR
  • IEEE Trans Compon Packag Technol
  • 2002
2 Excerpts

Impact of solder pad size on solder joint reliability in flip chip PBGA packages

  • LL Mercador, V Sarihan, Y Guo, A. Mawer
  • IEEE Trans Adv Packag 2000;23:415–20
  • 2000
1 Excerpt

On enhancing eutectic solder joint reliability using a second-reflow-process approach

  • KN Chiang, YT Lin, HC. Cheng
  • IEEE Trans Adv Packag
  • 2000

Wafer level chip scale packaging (WL-CSP): an overview

  • P. Garrou
  • IEEE Trans Adv Packag
  • 2000

Design and analysis of experiments

  • DC Montgomery
  • New York: - Wiley;
  • 1991
1 Excerpt

Prediction of temperature cycling life for SMT solder joints on CTE-mismatched substrate

  • DE Riemer
  • Proceedings of 40th electronic components and…
  • 1990
1 Excerpt

Similar Papers

Loading similar papers…