Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture

Abstract

The TMS320C6000 architecture is a leading family of Digital Signal Processors (DSPs). To achieve peak performance, this VLIW architecture relies heavily on software pipelining. Traditionally, software pipelining has been restricted to <i>regular</i> (FOR) loops. More recently, software pipelining has been extended to <i>irregular</i> (WHILE) loops, but only… (More)
DOI: 10.1145/384197.384216

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