Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks

  title={Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks},
  author={Dimitrios Skarlatos and Renji Thomas and Aditya Agrawal and Shibin Qin and Robert Carl Nikolai Pilawa-Podgurski and Ulya R. Karpuzcu and Radu Teodorescu and Nam Sung Kim and Josep Torrellas},
  journal={2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)},
The pin count largely determines the cost of a chip package, which is often comparable to the cost of a die. In 3D processor-memory designs, power and ground (P/G) pins can account for the majority of the pins. This is because packages include separate pins for the disjoint processor and memory power delivery networks (PDNs). Supporting separate PDNs and P/G pins for processor and memory is inefficient, as each set has to be provisioned for the worst-case power delivery requirements. In this… CONTINUE READING


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