Smart imagers of the future

  title={Smart imagers of the future},
  author={Antoine Dupret and Micha{\"e}l Tchagaspanian and Arnaud Verdant and Laurent Alacoque and Arnaud Peizerat},
  journal={2011 Design, Automation & Test in Europe},
This paper presents the evolutions of CMOS image sensors. From the early works, highly image processing oriented, the main research effort has then emphasized on image acquisition. To overcome the rising limitations of standard approaches and to promote new functionalities, several research directions are underway with promising results. 

From This Paper

Figures, tables, and topics from this paper.


Publications citing this paper.
Showing 1-9 of 9 extracted citations

Neural Monitoring With CMOS Image Sensors

Basic and clinical neuroscience • 2018
View 4 Excerpts
Highly Influenced

An ASIP-based control system for Vision Chips with highly parallel signal processing

2015 IEEE 24th International Symposium on Industrial Electronics (ISIE) • 2015
View 1 Excerpt

Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) • 2015
View 2 Excerpts

Nonuniform sampling with adaptive expectancy based on local variance

2015 International Conference on Sampling Theory and Applications (SampTA) • 2015
View 1 Excerpt

On adaptive pixel random selection for compressive sensing

2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP) • 2014
View 1 Excerpt


Publications referenced by this paper.
Showing 1-10 of 33 references

A 25 mu m pitch LWIR focal plane array with pixellevel 15-bit ADC providing high well capacity and targeting 2mK NETD

F. Guellec, A. Peizerat, +9 authors Peyrard J.-C
Proc. SPIE 7660, • 2010
View 13 Excerpts
Highly Influenced

Silicon retina with adaptive photodetectors

M. A. Mahowald
Proc. SPIE, Visual Information Processing : From Neurons to Chips, • 1991
View 4 Excerpts
Highly Influenced

The optical mouse, and an architectural methodology for smart digital sensors

R. F. Lyon
View 15 Excerpts
Highly Influenced

A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture

2010 IEEE International Solid-State Circuits Conference - (ISSCC) • 2010
View 3 Excerpts

Digital processor array implementation aspects of a 3D multi-layer vision architecture

2010 12th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2010) • 2010

On-chip compression for HDR image sensors

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) • 2010
View 1 Excerpt

8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SA-ADC

IEEE Transactions on Electron Devices • 2009
View 2 Excerpts

A small footprint, streaming compliant, versatile wavelet compression scheme for cameraphone imagers

L. Alacoque, L Chotard
Proceedings of the 2009 International Image Sensor Workshop, • 2009

Similar Papers

Loading similar papers…