Small Delay Fault Model for Intra-Gate Resistive Open Defects

  title={Small Delay Fault Model for Intra-Gate Resistive Open Defects},
  author={Masayuki Arai and Akifumi Suto and Kazuhiko Iwasaki and Katsuyuki Nakano and Michihiro Shintani and Kazumi Hatayama and Takashi Aikyo},
  journal={2009 27th IEEE VLSI Test Symposium},
We propose the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering… CONTINUE READING

From This Paper

Figures, tables, results, connections, and topics extracted from this paper.
4 Extracted Citations
13 Extracted References
Similar Papers

Referenced Papers

Publications referenced by this paper.
Showing 1-10 of 13 references

Advances in Electronic Testing: Challenges and Methodologies, Springer-Verlag

  • D. Gizopoulos
  • 2006
2 Excerpts

Similar Papers

Loading similar papers…