Small Delay Fault Model for Intra-Gate Resistive Open Defects

@article{Arai2009SmallDF,
  title={Small Delay Fault Model for Intra-Gate Resistive Open Defects},
  author={Masayuki Arai and Akifumi Suto and Kazuhiko Iwasaki and Katsuyuki Nakano and Michihiro Shintani and Kazumi Hatayama and Takashi Aikyo},
  journal={2009 27th IEEE VLSI Test Symposium},
  year={2009},
  pages={27-32}
}
We propose the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering… CONTINUE READING

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