Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications

@article{Schiavone2017SlowAS,
  title={Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications},
  author={Pasquale Davide Schiavone and Francesco Conti and Davide Rossi and Michael Gautschi and Antonio Pullini and Eric Flamand and Luca Benini},
  journal={2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)},
  year={2017},
  pages={1-8}
}
Achieving a power envelope of few milliwatts combined with tight performance constraints is emerging as one of the key challenges for battery-powered and low cost Internet-of-things (IoT) end-nodes. [...] Key Result Micro-riscy is 1.6× smaller than Zero-riscy (∼11.6 kgates in UMC 65nm), has a power envelope of just 100μW at 160MHz and it is 1.4× more energy efficient than Zero-riscy on pure control code.Expand
LoTTA: Energy-Efficient Processor for Always-On Applications
TLDR
LoTTA is an extremely energy-efficient exposed datapath core that helps in lowering the execution latency via low cost data forwarding and an instruction register file is included for frequently executed program hot spots to reduce the instruction stream energy consumption. Expand
Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications
TLDR
Three multi-issue core designs featuring an exposed datapath architecture with high performance, while retaining energy-efficiency are proposed, achieved with exploitation of instruction-level parallelism, fast branching and the use of an instruction register file. Expand
An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture
TLDR
This paper proposed an ultra-low-power processor with variable micro-architecture based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode, which could improve energy efficiency in low-workload scenarios. Expand
Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing
TLDR
Mr Wolf is presented, a Parallel Ultra Low Power (PULP) SoC featuring a hierarchical architecture with a small microcontroller class RISC-V core augmented with an autonomous IO subsystem for efficient data transfer from a wide set of peripherals, enabling energy-proportional heterogeneous computing for always-ON IOT end-nodes. Expand
RISC-V Resource-Constrained Cores: A Survey and Energy Comparison
  • Islam Elsadek, E. Tawfik
  • Computer Science
  • 2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)
  • 2021
TLDR
This study targets to survey open-source RISC-V cores and classify them as high-performance and resource-constrained, and proposes a method to evaluate the energy consumption using power and performance values. Expand
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing
TLDR
The capabilities of the proposed SoC are demonstrated on a wide set of near-sensor processing kernels showing that Mr.Wolf can deliver performance up to 16.4 GOp/s with energy efficiency up to 274 MOp/S/mW on real-life applications, paving the way for always-on data analytics on high-bandwidth sensors at the edge of the Internet of Things. Expand
A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing
TLDR
This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers, tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. Expand
A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing
TLDR
This work exploits recent progress in high-SNR IMC to achieve a programmable heterogeneous microprocessor architecture implemented in 65-nm CMOS and corresponding interfaces to the software that enables mapping of application workloads. Expand
Modular Memory System for RISC-V Based MPSoCs on Xilinx FPGAs
TLDR
This paper presents a modular hybrid memory system for a lightweight RISC-V based MPSoC architecture, which consists of a global scratchpad on-chip shared memory for both instruction and data for the purpose of communication and synchronization between the processing elements. Expand
Open-Source RISC-V Processor IP Cores for FPGAs — Overview and Evaluation
TLDR
This work wants to focus on open-source 32-bit CPU IP cores suitable for FPGAs and which support the upcoming free and open RISC-V instruction set architecture that has some interesting advantages when compared to commercial CPU cores. Expand
...
1
2
3
4
5
...

References

SHOWING 1-10 OF 32 REFERENCES
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
TLDR
This paper describes the design of an open-source RISC-V processor core specifically designed for NT operation in tightly coupled multicore clusters, and introduces instruction extensions and microarchitectural optimizations to increase the computational density and to minimize the pressure toward the shared-memory hierarchy. Expand
A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI
TLDR
This paper presents a RISC-V system-on-chip (SoC) with integrated voltage regulation, adaptive clocking, and power management implemented in a 28 nm fully depleted silicon- on-insulator process, demonstrating practical microsecond-scale power management for mobile SoCs. Expand
The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor
Abstract : BOOM is a synthesizable, parameterized, superscalar out-of-order RISC-V core designed to serve as the prototypical baseline processor for future micro-architectural studies of out-of-orderExpand
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits
TLDR
The barriers to the widespread adoption of near-threshold computing are explored and current work aimed at overcoming these obstacles are described. Expand
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
TLDR
Fulmine, a system-on-chip (SoC) based on a tightly-coupled multi-core cluster augmented with specialized blocks for compute-intensive data processing and encryption functions, supporting software programmability for regular computing tasks is proposed. Expand
SleepWalker: A 25-MHz 0.4-V Sub- $\hbox{mm}^{2}$ 7- $\mu\hbox{W/MHz}$ Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes
  • D. Bol, J. Vos, +5 authors J. Legat
  • Engineering, Computer Science
  • IEEE Journal of Solid-State Circuits
  • 2013
TLDR
The SleepWalker microcontroller is a 65-nm ultralow-voltage SoC based on the MSP430 architecture capable of delivering increased speed performances at 25 MHz for only 7 μW/MHz at 0.4 V, and incorporates an on-chip adaptive voltage scaling (AVS) system with DC/DC converter, clock generator, memories, sensor and communication interfaces, making it suited for WSN applications. Expand
Ultra-Low-Power Digital Architectures for the Internet of Things
TLDR
This chapter provides a review of the state of the art Ultra-Low-Power (ULP) micro-controllers architecture, highlighting main challenges and perspectives, and introducing the potential of exploiting parallelism in this field currently dominated by single issue processors. Expand
Enabling the Internet of Things: From Integrated Circuits to Integrated Systems
This book offers the first comprehensive view on integrated circuit and system design for the Internet of Things (IoT), and in particular for the tiny nodes at its edge. The authors provide a freshExpand
Energy-efficient vision on the PULP platform for ultra-low power parallel computing
TLDR
This work proposes PULP (Parallel processing Ultra-Low Power platform), an architecture built on clusters of tightly-coupled OpenRISC ISA cores, with advanced techniques for fast performance and energy scalability that exploit the capabilities of the STMicroelectronics UTB FD-SOI 28nm technology. Expand
A −1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology
A 4-core cluster fabricated in low power 28nm UTBB FD-SOI conventional well technology is presented. The SoC architecture enables the processors to operate “on-demand” on a 0.44V (1.8MHz) to 1.2VExpand
...
1
2
3
4
...