• Corpus ID: 3712157

Skewed Branch Predictors

  title={Skewed Branch Predictors},
  author={Pierre Michaud and Andr{\'e} Seznec and Richard Uhlig},
As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on good branch prediction. During the past five years, researchers have shown that branch-prediction accuracy can be improved by basing predictions on the outcome of previous branches. Many such methods have been proposed, but they all share a common characteristic: they require hardware resources to implement the tables and state machines that record the branch… 
Evaluating Branch Predictors on an SMT Processor
This paper evaluates several wellknown branch prediction schemes, and examines some modifications to address problems caused by sharing of branch prediction hardware in SMT.
Scalable and energy efficient instruction scheduling
This dissertation presents an accurate, lookahead prediction of memory latency, which correctly predicts the latencies of 83% of the cache misses, and 98% ofthe cache hits, and applies a simple structure that sorts instructions in their expected issue order based on the predicted waiting time.
Implementación de una plataforma HW para la evaluación de predictores e saltos sobre arquitectura SPARC v8
Los predictores de salto supusieron una gran via de investigacion para la rama de la informatica dedicada al estudio e investigacion de la arquitectura de los computadores. Su principal objetivo,


Improving the accuracy of dynamic branch prediction using branch correlation
A correlation-based scheme that uses the information provided by a proper subhistory of a branch to predict the outcome of that branch, and the accuracy of the new scheme surpasses that of the counter–based branch predction at saturation.
Correlation and Aliasing in Dynamic Branch Predictors
It is shown that for predictors with small available resources, aliasing between distinct branches can have the dominant influence on prediction accuracy, and the simple scheme of selecting a predictor using the branch address can be more effective than more elaborate correlating branch predictors.
Combining Branch Predictors
This paper describes a method of increasing the usefulness of branch history by hashing it together with the branch address and shows that this new approach allows predictors with a single level of history array access to outperform schemes with multiple levels of history for all but the largest predictor sizes.
Skewed associativity enhances performance predictability
  • F. Bodin, André Seznec
  • Computer Science
    Proceedings 22nd Annual International Symposium on Computer Architecture
  • 1995
It is shown that the recently proposed four-way skewed associative cache yields very stable execution times and good average miss ratios on blocked algorithms, and it is possible to use larger blocks sizes with blocking algorithms, which will furthermore reduce blocking overhead costs.
An Analysis of Dynamic Branch Prediction Schemes on System Workloads
It is found that user-only traces yield accurate prediction results only when the kernel accounts for less than 5% of the total executed instructions, and that flushing the branch history state at fixed intervals does not accurately model the true effects of user/kernel interaction.
Aspects of cache memory and instruction buffer performance
Techniques are developed in this dissertation to efficiently evaluate direct-mapped and set-associative caches and examine instruction caches for single-chip RISC microprocessors, and it is demonstrated that instruction buffers will be preferred to target instruction buffers in future RISCmicroprocessors implemented on single CMOS chips.
A study of branch prediction strategies
First, currently used techniques are discussed and analyzed using instruction trace data, and new techniques are proposed and are shown to provide greater accuracy and more flexibility at low cost.
Skewed-associative Caches
In order to improve cache hit ratios, set-associative caches are used in some of the new superscalar microprocessors.
A case for two-way skewed-associative caches
Two-way skewed associative caches represent the best tradeoff for today microprocessors with on-chip caches whose sizes are in the range of 4-8K bytes.
A comparative analysis of schemes for correlated branch prediction
A framework is presented that categorizes branch prediction schemes by the way in which they partition dynamic branches and by the kind of predictor that they use, to show how a static correlated branch prediction scheme increases branch bias and thus improves overall branch prediction accuracy.