Skew aware polarity assignment in clock tree

  title={Skew aware polarity assignment in clock tree},
  author={Po-Yuan Chen and Kuan-Hsien Ho and TingTing Hwang},
  journal={2007 IEEE/ACM International Conference on Computer-Aided Design},
In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Althogh peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities… CONTINUE READING
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