Single Event Upset Mitigation Techniques for SRAM-based FPGAs

  title={Single Event Upset Mitigation Techniques for SRAM-based FPGAs},
  author={F. J. de Paula Lima and Luigi Carro and R. Reis},
This paper discusses high level techniques for designing fault tolerant systems in SRAM-based FPGAs, without modification in the FPGA architecture. TMR has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However, TMR comes with high area and power dissipation penalties. The new technique proposed in this paper was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while… CONTINUE READING