Single Cycle Tree 64 Bit Binary Comparator with Constant Delay Logic 1 Lavanya

  • LAVANYA.D, MANIKANDAN.T
  • Published 2015

Abstract

In this project, Single cycle tree based RADIX 4 stuructures 64 bit binary comparator with constant delay logic for reducing power its realized in a 65nm techonology 1-v CMOS process is presented in this paper. This design can be done by using Tanner tool with single cycle two comparator using Priority encoder algorithm. The proposed comparator architecture… (More)

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