Simultaneous scheduling and binding for power minimization during microarchitecture synthesis


Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the e ect of long interconnects and buses, compared to that of gates, on the overall performance, and energy of systems [13]. Consequently, we propose a RT level design technique to reduce the energy dissipated in switching of the buses ( 40% of the on… (More)
DOI: 10.1145/224081.224094


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