Simultaneous gate sizing and placement

  title={Simultaneous gate sizing and placement},
  author={Wei Chen and Cheng-Ta Hsieh and Massoud Pedram},
  journal={IEEE Trans. on CAD of Integrated Circuits and Systems},
In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. More precisely in each iteration, we perform three operations: a) reposition the immediate fan-outs of the gates on the k… CONTINUE READING
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Y.Ye, " An infeasible interior-point algorithm for solving primal and dual geometric programs

  • K. O. Kortanek, X. Xu
  • Mathematical Programming
  • 1996
1 Excerpt

Ettelt, "SPEED: Fast and Efficient Timing Driven Placement

  • G.G.B.M. Riess
  • Proc. Intl. Symposium of Circuits and Systems ,
  • 1995
1 Excerpt

I.N.Hajj, “Delay and Area Optimization for Compact Placement by Gate Resizing and Relocation

  • W. Chuang
  • Proc. Intl. Conf. on CAD,
  • 1994
1 Excerpt

Area-Power-Delay Trade-off in Logic Synthesis

  • M. Berkelaar
  • Ph.D Thesis, Eindhoven University of Technology,
  • 1992
1 Excerpt

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