Simultaneous block and I/O buffer floorplanning for flip-chip design

@article{Peng2006SimultaneousBA,
  title={Simultaneous block and I/O buffer floorplanning for flip-chip design},
  author={Chih-Yang Peng and Wen-Chang Chao and Yao-Wen Chang and Jyh-Herng Wang},
  journal={Asia and South Pacific Conference on Design Automation, 2006.},
  year={2006},
  pages={6 pp.-}
}
The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip-chip designs is that the input/output buffers could be placed anywhere inside a chip. In this paper, we first introduce the floorplanning problem for the flip-chip design and formulate it as assigning the positions of input/output buffers and first-stage/last-stage blocks so that the path length between blocks and bump balls as… CONTINUE READING

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Key Quantitative Results

  • Compared with the B*-tree based floorplanner alone, our method is more efficient and obtains significantly better results, with an average cost of only 51.8% of that obtained by using the B*-tree alone, based on a set of real industrial flip-chip designs provided by leading companies.
  • Compared with the B*-tree based .oorplanner alone, our method is more ef.cient and obtains signi.cantly bet­ter results, with an average cost of only 51.8% of that obtained by using the B*-tree alone, based on a set of real industrial .ip-chip designs provided by leading companies.
  • Compared with the B*-tree based .oorplanner alone, our method obtains signi.cantly better results, with an average cost of only 51.8% of that obtained by using the B*-tree alone, based on a set of real industrial .ip-chip designs provided by leading companies.

Citations

Publications citing this paper.
SHOWING 1-10 OF 12 CITATIONS

Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs

  • ACM Trans. Design Autom. Electr. Syst.
  • 2016
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CITES BACKGROUND, METHODS & RESULTS
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Timing-constrained I/O buffer placement for flip-chip designs

  • 2011 Design, Automation & Test in Europe
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Area-I/O RDL routing for chip-package codesign considering regional assignment

  • 2010 IEEE Electrical Design of Advanced Package & Systems Symposium
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An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign

  • 9th International Symposium on Quality Electronic Design (isqed 2008)
  • 2008
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CITES RESULTS, BACKGROUND & METHODS
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Signal skew aware floorplanning and bumper signal assignment technique for flip-chip

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  • 2009
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Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Multiple chip planning for chip-interposer codesign

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)
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Unified Padring Design Flow

  • 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks
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A chip-package-board co-design methodology

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Wirelength driven I/O buffer placement for flip-chip with timing-constrained

  • 2012 IEEE Asia Pacific Conference on Circuits and Systems
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